Why use ETSerdesTM to Test High-Speed Serial I/Os?

Serializer/deserializer (SerDes) transceivers are an increasingly popular way to reduce IC pin-count, power, electromagnetic interference, and wiring between ICs. Mainstream serial data rates are around 2.5 Gbps, with PCI-Express being the most common standard, but 5 to 10 Gbps SerDes I/Os are in many new designs. The total number of such transceivers shipped (there may be many per IC) is expected to exceed 1 billion in 2008. Testing these functions is accomplished in many ways, ranging from simply connecting a transmitter and receiver and checking for zero bit errors in half a second, to using top-of-the-line automatic test equipment (ATE) that can measure near-picosecond jitter so that the bit error rate (BER) can be estimated and compared to the industry-standard one error per trillion bits. Some third-party SerDes suppliers provide built-in parametric test solutions to avoid the complexity and expense of high-performance ATE-based testing. While these built-in approaches permit quick observation of signals in-system, they have shortcomings that can significantly affect yield if used for production testing of ICs, and lack important diagnostic capabilities when used in-system. LogicVision's ETSerdes comprises purely digital circuitry that is embedded in an IC's design, at the RTL level, and provides comprehensive automation for synthesizing the circuitry and generating a suite of Verilog-simulatable structural tests suitable for manufacturing process characterization and go/no-go testing. Sub-picosecond accuracy can be achieved with tests that take less than a few hundred milliseconds and run on any ATE, even on a laptop PC in the relative quiet of a designer's office. ETSerdes can significantly reduce test costs by allowing any ATE to test any number of SerDes running at any serial data rate. The automated generation and simulation of a complete test suite in Verilog in only a few hours, and the use of the timing-insensitive JTAG test access port for all communications with the ATE, ensures that first silicon can be verified in hours instead of weeks. Compared to simple loopback testing, on-chip testing with ETSerdes permits tracking parameter values to uniquely detect and help diagnose yield or quality losses before they become catastrophic. For systems with SerDes operating above 4 Gbps, the dominant source of jitter and bit errors is the limited bandwidth of the wire path. The primary compensating mechanism for this jitter is equalization in the receiver yet its impact cannot be directly observed with external equipment. ETSerdes provides fast and unique diagnostic characterization of equalization …